Silicon & Architecture / Midday Architecture / Nov 05, 2026, 12:00 PM IST

The Shockley Diode & The PNPN Negative Resistance Anomaly

§ FIRST PRINCIPLES GOVERNING LAW

Charge carrier avalanche injection across a reverse-biased PN junction enables regenerative current gain exceeding unity ( $α_{1} + α_{2} \geq 1$ $α_{2} \geq$ $1$ ), triggering abrupt negative dynamic resistance and bistable latching.

THE BENTO BRIDGE From Discrete Hardware Artifact to Modern Micro-Architecture

THEN Historical Prototype (1956)

Discrete four-layer p-n-p-n gold-doped silicon mesa diodes hand-packaged into TO-5 metal cans for telephone crossbar exchange switching.

NOW Sub-3nm Silicon Integration

Monolithic silicon-controlled rectifier (SCR) and transient voltage suppression (TVS) structures integrated adjacent to FinFET I/O bonding pads.

MATHEMATICAL PROOF

Regenerative Latch Condition in a Four-Layer PNPN Junction

Total Anode Current

I_A = \alpha_1 I_A + \alpha_2 I_K + I_{CO}

Sum of forward emitter-collector currents across junctions J1 and J3.

Regenerative Criterion

I_A = \frac{I_{CO}}{1 - (\alpha_1 + \alpha_2)}

When sum of common-base gains (α1 + α2) approaches unity, the denominator approaches zero, triggering avalanche switching.

Breakover Voltage Scaling

V_{BO} = V_{BD} \cdot \sqrt[n]{1 - \alpha_1 - \alpha_2}

Avalanche multiplication factor M scales with applied voltage until the device snaps back into low-impedance conduction.

Historical Context & The 1956 Breakthrough

In 1956, William Shockley founded Shockley Semiconductor Laboratory in Mountain View, California—an event widely recognized as the geographical genesis of Silicon Valley. While his team included brilliant minds like Robert Noyce, Gordon Moore, and Jean Hoerni, Shockley became fixated on creating a four-layer diode switch that could replace mechanical telephone crossbar switches.

First Principles Physical Mechanics

The PNPN structure consists of three consecutive PN junctions in series ( $J_1$ , $J_2$ , and $J_3$ ). In the forward-blocking state:

Junctions $J_1$ and $J_3$ are forward-biased.
The central junction $J_2$ is reverse-biased, supporting virtually the entire applied anode-cathode voltage.

As the applied voltage increases toward the breakover threshold $V_{BO}$ , impact ionization within the depletion layer of $J_2$ multiplies electron-hole pairs. Because the structure can be analyzed as two coupled bipolar transistors ( $p-n-p$ and $n-p-n$ ) sharing collector-base regions, the internal feedback loop drives both transistors into heavy saturation once:

$\alpha_1 + \alpha_2 \ge 1$

HARDWARE AVALANCHE SIMULATION

PNPN Dynamic Negative Resistance IV Curve Simulation

AUTO-SLEEP ON BACKGROUND

STATE: FORWARD BLOCKING

ANODE VOLTAGE (V_A): 35.0 V

ANODE CURRENT (I_A): 0.12 mA

DYNAMIC RESISTANCE: +8.5 MΩ

$49USD

Discrete 4-Layer Avalanche Laboratory Bench Kit

Comprehensive laboratory kit containing matched 2N5060 thyristors, curve-tracer probe points, high-speed oscilloscope fixture PCB, and complete bench schematics.

✓Matched discrete laboratory components, probe headers, & test fixture PCB

✓KiCad schematics, Gerber manufacturing files, & SPICE verification models

✓Step-by-step laboratory verification protocol & calibration rubric

RAZORPAY / STRIPE

UPI (GPay, PhonePe, Paytm), Cards & NetBanking

⚡Acquire Laboratory Vault & Schematics→Instant ZIP Download + Global Hardware Kit Shipping

Preview: 00_FIRST_TIME_SETUP_GUIDE.md

View Instructions

# 00_FIRST_TIME_SETUP_GUIDE.md
## Bench Safety & High-Impedance Latch Characterization
1. Connect Current-Limiting Resistor (R_LIMIT = 10kΩ, 2W) in series with Device Under Test (DUT).
2. Set programmable DC source sweep rate to 0.5V/step up to 60V max.
3. Monitor Junction J2 displacement current using high-bandwidth differential probe on CH1.
4. Confirm transition to negative resistance when dV/dI flips from positive to negative.