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Intel 4004: The World's First Single-Chip Microprocessor

§ FIRST PRINCIPLES GOVERNING LAW

Unifying the arithmetic logic unit, program counter, and micro-instruction control circuitry onto a single semiconductor substrate eliminates inter-chip capacitive pin delays.

THE BENTO BRIDGE From Discrete Hardware Artifact to Modern Micro-Architecture
THEN Historical Prototype (1971)

2,300 PMOS silicon-gate transistors in a 16-pin dual in-line package (DIP) clocked at 740 kHz on a 10-micrometer planar process.

NOW Sub-3nm Silicon Integration

Over 50 billion FinFET and Gate-All-Around (GAA) nanosheet transistors per monolithic die executing out-of-order superscalar pipelines above 5 GHz.

MATHEMATICAL PROOF

Interconnect Capacitance Scaling & Microprocessor Timing Budgets

Off-Chip vs On-Die Pin Capacitance Ratio
CpinCgate=10×10−12 F10×10−15 F≈103\frac{C_{\text{pin}}}{C_{\text{gate}}} = \frac{10 \times 10^{-12} \text{ F}}{10 \times 10^{-15} \text{ F}} \approx 10^3

Packaging pins and printed-circuit traces carry picofarads of parasitic capacitance, whereas on-die silicon interconnects carry femtofarads, creating a 1000x energy and delay penalty for multi-chip buses.

Dynamic Bus Charging Energy
Ecycle=12CloadVDD2E_{\text{cycle}} = \frac{1}{2} C_{\text{load}} V_{DD}^2

Charging external PCB interconnect traces at 12V V_DD consumes orders of magnitude more energy than on-chip gate toggling.

Microprocessor Clock Timing Budget
Tclk≥tsetup+tprop,ALU+tskew+tjitterT_{\text{clk}} \ge t_{\text{setup}} + t_{\text{prop,ALU}} + t_{\text{skew}} + t_{\text{jitter}}

The minimum clock cycle period is bounded by register setup times, maximum combinational logic propagation delay across the ALU, and clock skew.

Elmore Interconnect Propagation Delay
τElmore=∑k=1NRk∑j∈subtree(k)Cj\tau_{\text{Elmore}} = \sum_{k=1}^N R_k \sum_{j \in \text{subtree}(k)} C_j

Distributed RC line delay governs signal transmission across silicon metal layers, favoring localized compact datapath floorplans.

1. Executive Summary & Historical Provenance

In 1969, Japanese calculator company Busicom contracted the nascent Intel Corporation to design a custom set of 12 integrated circuits for their upcoming printing desktop calculator. Intel engineer Ted Hoff recognized that building 12 specialized chips was economically unviable and technically fragile. Instead, Hoff and Stan Mazor proposed a radical architecture: a general-purpose 4-bit computer whose functionality would be dictated entirely by software stored in ROM.

The challenge of converting this architectural proposal into working silicon fell to Federico Faggin. Faggin, who had developed the self-aligned silicon-gate MOS process at Fairchild, arrived at Intel in April 1970. Working grueling 80-hour weeks with Japanese engineer Masatoshi Shima, Faggin invented “buried contacts” (direct silicon-to-polysilicon connections without metal contacts) and bootstrapped load drivers. In March 1971, the first functional silicon dies were tested. Announced commercially in November 1971 in Electronic News, the Intel 4004 marked the birth of the single-chip microprocessor.

2. First Principles Governing Physics

Why was moving the CPU onto a single monolithic die such a transformative physical leap? The answer lies in the physics of electrical parasitics and charge transfer:

  1. The Parasitic Pin Wall: In a multi-chip system, every communication between the register file, ALU, and control unit must cross chip bonding wires, package leads, and PCB copper traces. A typical package pin exhibits 5 to 15 pF of parasitic capacitance and several nanohenries of inductance. On-chip metal interconnects, by contrast, exhibit sub-femtofarad capacitances.
  2. Dynamic Energy Dissipation: Charging and discharging a capacitive node dissipates E=12CV2E = \frac{1}{2} C V^2. By keeping the register files and arithmetic logic inside the die boundaries, Faggin reduced the capacitive load of critical feedback paths by three orders of magnitude.
  3. Silicon-Gate PMOS Speed Advantage: Older aluminum-gate MOS processes required wide tolerances to prevent gate-drain alignment overlap, resulting in massive parasitic gate-to-drain Miller capacitance (CgdC_{gd}). Faggin’s self-aligned polysilicon gate eliminated this overlap, accelerating switching speed by a factor of five while cutting die area by half.

3. The Bento Bridge: From Discrete Artifact to Sub-3nm Monolithic Silicon

  • Then (1971): 2,300 PMOS transistors hand-drawn on mylar drafting sheets, digitized by rubylith, running at 740 kHz on a 10,000 nm (10 µm) process with a 12V to 15V supply in a ceramic 16-pin package.
  • Now (Modern Monolithic Silicon): Multi-core 64-bit processors with over 50 billion FinFET and GAA nanosheet transistors per package, operating at sub-0.8V supply rails with 5+ GHz clock domains, executing complex branch prediction, vector matrix extensions, and out-of-order instruction scheduling.

The foundational truth established by Faggin and the Intel 4004 team remains absolute: the shortest, lowest-capacitance wire is the wire that never leaves the silicon crystal.

HARDWARE AVALANCHE SIMULATION

Intel 4004 Microarchitecture Bus & Sub-Cycle State Simulation

AUTO-SLEEP ON BACKGROUND
STATE: FORWARD BLOCKING
ANODE VOLTAGE (V_A): 35.0 V
ANODE CURRENT (I_A): 0.12 mA
DYNAMIC RESISTANCE: +8.5 MΩ
35.0 V