OPEN HARDWARE RESEARCH BLOG / Electronics · Silicon
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StudyHour

First-principles engineering, hardware heritage, and interactive silicon simulations.

StudyHour

First-principles engineering, hardware heritage, and interactive silicon simulations.

PRINT-READY ENGINEERING CHEAT SHEET · REVISION 2026.1

Silicon, SPICE & Microarchitecture Reference Sheet

First-principles governing equations, semiconductor device physics, sub-3nm timing constraints, and parallel compute scaling parameters. Optimized for bench verification, laboratory pin-ups, and architectural timing analysis.

Open Interactive Simulators →
01

Electrodynamics & Continuous Wave Fields

Field equations, displacement currents & transmission velocity
Simulate ↗
Ampère-Maxwell Circuital Law
∇×B⃗=μ0(J⃗+ε0∂E⃗∂t)∇×B⃗=μ0(J⃗+ε0∂E⃗∂t)\nabla \times \vec{B} = \mu_0 \left(\vec{J} + \varepsilon_0 \frac{\partial \vec{E}}{\partial t}\right)
Displacement current density J_D = ε₀ · ∂E/∂t satisfies charge continuity across dielectric boundaries.
Phase Velocity & Intrinsic Medium Impedance
vp=1μ0εrε0=cεr,η=με≈376.73εr Ωv_p = 1μ0εrε0=cεr\frac{1}{\sqrt{\mu_0 \varepsilon_r \varepsilon_0}} = \frac{c}{\sqrt{\varepsilon_r}}, \quad \eta = με≈376.73εr Ω</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.7167em\sqrt{\frac{\mu}{\varepsilon}} \approx \frac{376.73}{\sqrt{\varepsilon_r}} \ \Omega</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.7167em;vertical-align:-0.2861em;">vp​=μ0​εr​ε0​​1​=εr​​c​,η=εμ​​≈εr​​376.73​ Ω
Determines signal propagation speed and high-speed inter-die trace characteristic impedance.
Poynting Energy Flux Vector
S⃗=1μ0(E⃗×B⃗),⟨S⟩=12∣E0∣2ηS⃗=1μ0(E⃗×B⃗)\vec{S} = \frac{1}{\mu_0} (\vec{E} \times \vec{B}), \quad \langle S \rangle = 12∣E0∣2η</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.9663em\frac{1}{2} \frac{|E_0|^2}{\eta}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.9663em;">S=μ0​1​(E×B),⟨S⟩=21​η∣E0​∣2​
Instantaneous directional power density transported per unit area across free space or dielectric channels.
02

Semiconductor Physics & PNPN Junctions

Carrier transport, depletion capacitance & regenerative latching
Simulate ↗
Shockley Ideal Diode Equation
ID=IS(eqVDnkBT−1),VT=kBTq≈25.86 mV @ 300KI_D = I_S (eqVDnkBT−1)\left( e^{\frac{q V_D}{n k_B T}} - 1 \right), \quad V_T = kBTq≈25.86 mV @ 300K</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.8333em\frac{k_B T}{q} \approx 25.86 \text{ mV @ 300K}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8333em;vertical-align:-0.15em;">ID​=IS​(enkB​TqVD​​−1),VT​=qkB​T​≈25.86 mV @ 300K
Forward injection and reverse generation-recombination current across abrupt PN junctions.
Depletion Capacitance & Built-In Barrier Potential
Vbi=VTln⁡(NANDni2),Cj=Cj01−VR/VbiV_{bi} = V_T \ln (NANDni2)\left(\frac{N_A N_D}{n_i^2}\right), \quad C_j = Cj01−VR/Vbi</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.8333em\frac{C_{j0}}{\sqrt{1 - V_R / V_{bi}}}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8333em;vertical-align:-0.15em;">Vbi​=VT​ln(ni2​NA​ND​​),Cj​=1−VR​/Vbi​​Cj0​​
Voltage-dependent reverse junction capacitance establishing ESD clamp and varactor tuning ranges.
4-Layer PNPN Regenerative Latching Criterion
IA=ICO1−(α1+α2)  ⟹  α1+α2≥1I_A = \frac{I_{CO}}{1 - (\alpha_1 + \alpha_2)} \implies α1+α2≥1</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.8333em\alpha_1 + \alpha_2 \ge 1</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8333em;vertical-align:-0.15em;">IA​=1−(α1​+α2​)ICO​​⟹α1​+α2​≥1
When the sum of internal transistor common-base current gains approaches unity, negative dynamic resistance triggers low-impedance latching.
03

CMOS Device Physics & Inverter Scaling

Saturation currents, transit delays & dynamic/static power
Simulate ↗
Square-Law Saturation Drain Current
ID,sat=12μnCoxWL(VGS−Vth)2(1+λchVDS)I_{D,\text{sat}} = \frac{1}{2} \mu_n C_{\text{ox}} \frac{W}{L} (V_{GS} - V_{th})^2 (1 + \lambda_{\text{ch}} V_{DS})
Channel conduction above pinch-off with channel-length modulation factor λ.
Intrinsic Gate Transit Time Metric (τ)
τ=Cggm=L2μ(VGS−Vth)\tau = \frac{C_g}{g_m} = \frac{L^2}{\mu (V_{GS} - V_{th})}
Theoretical switching speed limit for an unloaded minimum-sized MOSFET gate.
CMOS Dynamic Switching & Leakage Power
Ptotal=α⋅Ceff⋅VDD2⋅f+VDD⋅Ileak,EDP=Pdyn⋅texec2P_{\text{total}} = \alpha \cdot C_{\text{eff}} \cdot V_{DD}^2 \cdot f + V_{DD} \cdot I_{\text{leak}}, \quad EDP=Pdyn⋅texec2</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.8333em\text{EDP} = P_{\text{dyn}} \cdot t_{\text{exec}}^2</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8333em;vertical-align:-0.15em;">Ptotal​=α⋅Ceff​⋅VDD2​⋅f+VDD​⋅Ileak​,EDP=Pdyn​⋅texec2​
Quadratic dynamic voltage dependency governing Energy-Aware Scheduling (EAS) across heterogeneous dies.
04

Interconnect Scaling & Static Timing Analysis

Elmore RC delay, setup/hold slacks & logical effort
Simulate ↗
Elmore Distributed RC Delay
τElmore=∑k=1NRk∑j∈subtree(k)Cj\tau_{\text{Elmore}} = \sum_{k=1}^N R_k \sum_{j \in \text{subtree}(k)} C_j
Calculates first-moment signal delay through distributed RC interconnect metal layers.
Setup Slack & Hold Slack Timing Constraints
Slacksetup=Tclk−(tcq+tcomb,max+tsetup+tskew)≥0\text{Slack}_{\text{setup}} = T_{\text{clk}} - (t_{\text{cq}} + t_{\text{comb,max}} + t_{\text{setup}} + t_{\text{skew}}) ≥0</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.9805em\ge 0</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.9805em;vertical-align:-0.2861em;">Slacksetup​=Tclk​−(tcq​+tcomb,max​+tsetup​+tskew​)≥0
Slackhold=(tcq+tcomb,min)−(thold+tskew)≥0\text{Slack}_{\text{hold}} = (t_{\text{cq}} + t_{\text{comb,min}}) - (t_{\text{hold}} + t_{\text{skew}}) ≥0</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.8444em\ge 0</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8444em;vertical-align:-0.15em;">Slackhold​=(tcq​+tcomb,min​)−(thold​+tskew​)≥0
Bounds maximum operating frequency (f_max = 1 / T_clk,min) and prevents clock race conditions.
Optimal Inverter Chain Driving Ratio (Logical Effort)
f=CloadCinN,Dmin⁡=N⋅f⋅τ(optimum at f≈e≈2.72)f = CloadCinN\sqrt[N]{\frac{C_{\text{load}}}{C_{\text{in}}}}, \quad D_{\min} = N ⋅f⋅τ(optimum at f≈e≈2.72)\cdot f \cdot \tau \quad (\text{optimum at } f \approx e \approx 2.72)
Minimizes total propagation delay when driving large capacitive off-chip bus loads.
05

Parallel Compute & Roofline Bandwidth Model

Arithmetic intensity, DRAM throughput & memory walls
Simulate ↗
Operational / Arithmetic Intensity (I)
I=Total Floating-Point Operations (FLOPs)Total DRAM Traffic (Bytes Transferred)I = \frac{\text{Total Floating-Point Operations (FLOPs)}}{\text{Total DRAM Traffic (Bytes Transferred)}}
Characterizes the compute-to-communication ratio of a parallel kernel execution profile.
Attainable Hardware Throughput Bound
P=min⁡(Ppeak, I⋅Bmemory)P = \min\left(P_{\text{peak}}, \ I \cdot B_{\text{memory}}\right)
Identifies whether an algorithm is memory-bandwidth bound (I < I_ridge) or compute-bound (I ≥ I_ridge).
Amdahl's Law Speedup Limit
S(N)=1(1−p)+pN  ⟹  lim⁡N→∞S(N)=11−pS(N) = \frac{1}{(1 - p) + \frac{p}{N}} \implies \lim_{N \to \infty} S(N) = 11−p</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:1em\frac{1}{1 - p}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:1em;vertical-align:-0.25em;">S(N)=(1−p)+Np​1​⟹N→∞lim​S(N)=1−p1​
Theoretical maximum speedup for N parallel processing cores with serial fractional overhead (1 - p).
06

Physical Constants & Laboratory Metric Standards

Standard physical constants for semiconductor SPICE analysis
NIST Verified
Symbol Quantity Description Standard Numerical Value Units
q Elementary Elementary Charge 1.602 176 634 × 10⁻¹⁹ Coulombs (C)
k_B Boltzmann Constant 1.380 649 × 10⁻²³ J / K
c Speed of Light in Vacuum 2.997 924 58 × 10⁸ m / s
ε₀ Vacuum Electric Permittivity 8.854 187 8128 × 10⁻¹² F / m
µ₀ Vacuum Magnetic Permeability 1.256 637 062 × 10⁻⁶ (4π × 10⁻⁷) H / m (N / A²)
h Planck Constant 6.626 070 15 × 10⁻³⁴ J · s
ħ Reduced Planck Constant (h / 2π) 1.054 571 817 × 10⁻³⁴ J · s
V_T Thermal Voltage @ T = 300 K 0.025 852 Volts (25.85 mV)
n_i (Si) Silicon Intrinsic Carrier Density @ 300 K ~1.0 × 10¹⁰ cm⁻³