OPEN HARDWARE RESEARCH BLOG / Electronics · Silicon
IST (UTC+05:30)

StudyHour

First-principles engineering, hardware heritage, and interactive silicon simulations.

StudyHour

First-principles engineering, hardware heritage, and interactive silicon simulations.

INTERACTIVE ENGINEERING CALCULATORS & SIMULATORS

First-Principles Numerical Engines & Simulators

Explore standalone, browser-executable engineering calculators running 60 FPS HTML5 Canvas physical simulations, SPICE-correlated semiconductor curves, and VLSI timing closures directly derived from governing differential equations.

Electrodynamics Field Simulation
HTML5 Canvas (60 FPS Vector Field)

Maxwell Displacement Current & EM Wave Phase Velocity

Simulate time-varying displacement current densities JD=ε0∂E∂tJ_D = ε0∂E∂t</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.8333em\varepsilon_0 \frac{\partial E}{\partial t}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8333em;vertical-align:-0.15em;">JD​=ε0​∂t∂E​ through dielectric slabs and observe orthogonal transverse EE and BB wave propagation.

GOVERNING FIRST-PRINCIPLE FORMULATION
∇×B⃗=μ0(J⃗+ε0∂E⃗∂t),vp=cεr∇×B⃗=μ0(J⃗+ε0∂E⃗∂t)\nabla \times \vec{B} = \mu_0 \left(\vec{J} + \varepsilon_0 \frac{\partial \vec{E}}{\partial t}\right), \quad v_p = cεr</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.7667em\frac{c}{\sqrt{\varepsilon_r}}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.7667em;vertical-align:-0.0833em;">∇×B=μ0​(J+ε0​∂t∂E​),vp​=εr​​c​
SIMULATION SWEEPS & INPUT PARAMETERS:
  • Dielectric constant εrεr</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.5806em\varepsilon_r</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.5806em;vertical-align:-0.15em;">εr​ (Vacuum, SiO2SiO2</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.8333em\text{SiO}_2</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8333em;vertical-align:-0.15em;">SiO2​, HfO2HfO2</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.8444em\text{HfO}_2</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8444em;vertical-align:-0.15em;">HfO2​)
  • RF Carrier frequency (GHz)
  • Electric field drive (MV/mMV/m)
Historical Provenance: Maxwell's Displacement Current (1873)
Launch Simulator →
Semiconductors IV Characteristic Curve
Non-Linear Piecewise Numerical Model

4-Layer PNPN Thyristor Dynamic Breakover & Snapback

Plot the bistable non-linear IV curve of a Shockley 4-layer diode. Sweep anode bias to observe forward blocking, avalanche transition, and negative dynamic resistance.

GOVERNING FIRST-PRINCIPLE FORMULATION
IA=ICO1−(α1+α2),VBO=VBD⋅1−α1−α2nI_A = \frac{I_{CO}}{1 - (\alpha_1 + \alpha_2)}, \quad V_{BO} = V_{BD} ⋅1−α1−α2n</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.8333em\cdot \sqrt[n]{1 - \alpha_1 - \alpha_2}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8333em;vertical-align:-0.15em;">IA​=1−(α1​+α2​)ICO​​,VBO​=VBD​⋅n1−α1​−α2​​
SIMULATION SWEEPS & INPUT PARAMETERS:
  • Breakover voltage VBOV_{BO} (V)
  • Holding current IHI_H (mA)
  • Common-base gains α1+α2\alpha_1 + \alpha_2
Historical Provenance: Shockley Semiconductor 4-Layer Diode (1956)
Launch Simulator →
Semiconductors Regenerative Switching
Two-Transistor Feedback Numerical Model

Shockley 4-Layer Diode Regenerative Switching & Negative Resistance

Trace regenerative latching in 4-layer silicon p-n-p-n devices. Explore forward blocking, avalanche breakover at junction J2, and snapback into low-impedance conduction.

GOVERNING FIRST-PRINCIPLE FORMULATION
IA=MpICBO1+MnICBO21−(Mpα1+Mnα2),α1+α2≥1I_A = \frac{M_p I_{CBO1} + M_n I_{CBO2}}{1 - (M_p \alpha_1 + M_n \alpha_2)}, \quad α1+α2≥1</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.8333em\alpha_1 + \alpha_2 \ge 1</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8333em;vertical-align:-0.15em;">IA​=1−(Mp​α1​+Mn​α2​)Mp​ICBO1​+Mn​ICBO2​​,α1​+α2​≥1
SIMULATION SWEEPS & INPUT PARAMETERS:
  • Anode bias voltage VAV_A (V)
  • Breakover voltage VBOV_{BO} (50V to 100V)
  • Holding current IHI_H (mA)
Historical Provenance: Shockley Semiconductor Laboratory & 4-Layer Diode (1956)
Launch Simulator →
Modern Systems Microarchitecture
Energy-Aware Scheduler (EAS) Model

Heterogeneous big.LITTLE DVFS & Energy-Delay Optimizer

Calculate quadratic CMOS dynamic switching power vs frequency and evaluate the optimal thread migration policy between high-IPC Big cores and energy-efficient Little cores.

GOVERNING FIRST-PRINCIPLE FORMULATION
Pdyn=α⋅Ceff⋅VDD2⋅f,EDP=Pdyn⋅texec2P_{\text{dyn}} = \alpha \cdot C_{\text{eff}} \cdot V_{DD}^2 \cdot f, \quad EDP=Pdyn⋅texec2</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.9694em\text{EDP} = P_{\text{dyn}} \cdot t_{\text{exec}}^2</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.9694em;vertical-align:-0.2861em;">Pdyn​=α⋅Ceff​⋅VDD2​⋅f,EDP=Pdyn​⋅texec2​
SIMULATION SWEEPS & INPUT PARAMETERS:
  • Core microarchitecture (Cortex-X vs A520)
  • Clock frequency ff (0.5 to 3.5 GHz)
  • Supply voltage VDDV_{DD} (0.65 to 1.25 V)
Historical Provenance: Android ARM Linux Ecosystem (2007)
Launch Simulator →
VLSI & Timing Timing & Signal Integrity
Distributed RC Line Simulation

Intel 4004 Monolithic Bus & Elmore RC Interconnect Delay

Model the 1000x capacitive disparity between off-chip package pins and monolithic on-die metal tracks. Trace non-overlapping 2-phase clocking and minimum cycle period bounds.

GOVERNING FIRST-PRINCIPLE FORMULATION
τElmore=∑kRk∑j∈subtree(k)Cj,CpinCgate≈103\tau_{\text{Elmore}} = \sum_{k} R_k \sum_{j \in \text{subtree}(k)} C_j, \quad CpinCgate≈103</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.5806em\frac{C_{\text{pin}}}{C_{\text{gate}}} \approx 10^3</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.5806em;vertical-align:-0.15em;">τElmore​=k∑​Rk​j∈subtree(k)∑​Cj​,Cgate​Cpin​​≈103
SIMULATION SWEEPS & INPUT PARAMETERS:
  • Bus load capacitance CloadC_{\text{load}}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8333em;vertical-align:-0.15em;">Cload​ (pF)
  • Clock frequency fclkf_{\text{clk}}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8889em;vertical-align:-0.1944em;">fclk​ (kHz)
  • Logic propagation delay tpropt_{\text{prop}}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.9012em;vertical-align:-0.2861em;">tprop​
Historical Provenance: Intel 4004 Single-Chip Microprocessor (1971)
Launch Simulator →
VLSI & Timing Silicon Compilation
Logical Effort & DRC Scaling

Mead-Conway Scalable Lambda (λ) & Inverter Chain Sizing

Calculate the fundamental transit time metric ττ</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.4306em\tau</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.4306em;">τ, scale geometric design rules with parameter λ\lambda, and compute the optimal stage effort f≈ef ≈e</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.8889em\approx e</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8889em;vertical-align:-0.1944em;">f≈e for driving large capacitive loads.

GOVERNING FIRST-PRINCIPLE FORMULATION
τ=Cggm=L2μ(VGS−Vth),f=CloadCinN,Dmin=N⋅f⋅τ\tau = \frac{C_g}{g_m} = \frac{L^2}{\mu(V_{GS}-V_{th})}, \quad f = CloadCinN\sqrt[N]{\frac{C_{\text{load}}}{C_{\text{in}}}}, \quad D_{\text{min}} = N \cdot f \cdot \tau</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.4306em;">τ=gm​Cg​​=μ(VGS​−Vth​)L2​,f=NCin​Cload​​​,Dmin​=N⋅f⋅τ
SIMULATION SWEEPS & INPUT PARAMETERS:
  • Process feature scale λ\lambda (µm)
  • Inverter stage count NN
  • Capacitive fan-out ratio Cload/CinC_{\text{load}}/C_{\text{in}}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:1em;vertical-align:-0.25em;">Cload​/Cin​
Historical Provenance: Mead & Conway Structured VLSI Systems (1979)
Launch Simulator →
Electrodynamics Ionization Physics
Exponential Kinetics & Charge Balance

Curie Radioactive Decay & Piezoelectric Electrometer Balance

Model first-order radioactive population depletion and calculate the mechanical tension required for a piezoelectric quartz crystal to generate a neutralizing sub-picoampere current.

GOVERNING FIRST-PRINCIPLE FORMULATION
N(t)=N0e−λt,T1/2=ln⁡2λ,Iion=d11⋅dFdtN(t) = N_0 e^{-\lambda t}, \quad T_{1/2} = ln⁡2λ\frac{\ln 2}{\lambda}, \quad I_{\text{ion}} = d_{11} \cdot \frac{dF}{dt}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:1em;vertical-align:-0.25em;">N(t)=N0​e−λt,T1/2​=λln2​,Iion​=d11​⋅dtdF​
SIMULATION SWEEPS & INPUT PARAMETERS:
  • Isotope half-life T1/2T_{1/2} (Radium-226 vs Uranium)
  • Chamber air volume (cm3cm^3)
  • Piezoelectric modulus d11d_{11} (pC/NpC/N)
Historical Provenance: Marie Curie & Spontaneous Radiation (1867/1898)
Launch Simulator →
Electrodynamics RF Communications
Bessel Function Spectrum Analyzer

Armstrong Wideband FM Deviation & Carson's Bandwidth

Compute the spectral distribution of frequency-modulated carriers using Bessel functions of the first kind Jn(β)J_n(β\beta) and verify Carson's empirical 98%98\% transmission bandwidth limit.

GOVERNING FIRST-PRINCIPLE FORMULATION
s(t)=Accos⁡(2πfct+βsin⁡(2πfmt)),BT=2(Δf+fm)s(t) = A_c \cos(2\pi f_c t + βsin⁡(2πfmt)\beta \sin(2\pi f_m t)), \quad B_T = 2(\Delta f + f_m)
SIMULATION SWEEPS & INPUT PARAMETERS:
  • Carrier frequency fcf_c (MHz)
  • Frequency deviation Δf\Delta f (kHz)
  • Modulation index β=Δf/fmβ=Δf/fm</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.8889em\beta = \Delta f / f_m</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8889em;vertical-align:-0.1944em;">β=Δf/fm​
Historical Provenance: Edwin Armstrong Wideband FM (1935)
Launch Simulator →
Modern Systems High Performance Computing
Arithmetic Intensity & Bandwidth Model

GPU Streaming Multiprocessor Roofline Memory Wall Model

Determine whether a parallel compute kernel is memory-bandwidth bound or compute-bound by plotting arithmetic intensity (FLOPs/Byte) against peak hardware throughput.

GOVERNING FIRST-PRINCIPLE FORMULATION
P=min⁡(Ppeak,I⋅Bmemory),I=FLOPsDRAM BytesP = \min(P_{\text{peak}}, I ⋅Bmemory)\cdot B_{\text{memory}}), \quad I = FLOPsDRAM Bytes</annotation></semantics></math></span><spanclass="katex−html"aria−hidden="true"><spanclass="katex−base"><spanclass="katex−strut"style="height:0.6833em\frac{\text{FLOPs}}{\text{DRAM Bytes}}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.6833em;">P=min(Ppeak​,I⋅Bmemory​),I=DRAM BytesFLOPs​
SIMULATION SWEEPS & INPUT PARAMETERS:
  • Memory bandwidth BmemB_{\text{mem}}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.8333em;vertical-align:-0.15em;">Bmem​ (GB/s)
  • Peak compute capability PpeakP_{\text{peak}}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="katex-base"><span class="katex-strut" style="height:0.9694em;vertical-align:-0.2861em;">Ppeak​ (TFLOPs)
  • Kernel operational intensity II
Historical Provenance: NVIDIA CUDA Streaming Multiprocessor (2006)
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